NINTENDO HARDWARE REGISTERS


$2000 (PPU_Ctrl0)	PPU Control Register 0
	bit 7: VBlank NMI enable
	  if 1, enables VBlank NMIs.  Read $2002 to clear NMI after each VBlank.
	bit 6: Slave mode (MUST BE 0) 0=master, 1=slave.
	bit 5: Double sprite height
	  set to 1 to use 16-pixel tall sprites.  The least significant bit of
	  the character number of the sprite is ignored, and the character
	  thus specified and the next are stacked, top/bottom.
	bit 4: Background character set address
	  if 0, background characters are stored in $0000-$0FFF, or if 1, they
	  are stored in $1000-$1FFF.
	bit 3: Sprite character set address
	  if 0, sprite characters are stored in $0000-$0FFF, or if 1, they are
	  stored in $1000-$1FFF.
	bit 2: increment mode for PPU memory access
	  if 0, the PPU Address Register ($2006) will be incremented by 1 for
	  each PPU read or write.  If 1, the address will increment by 32.
	bit 1: MSB of vertical scroll offset
	  if 1, vertical scrolling will extend 240 pixels further down.  This
	  can access a second vertical page.  Note: do not set the vertical
	  scroll register to a value 240-255, use this bit instead.
	bit 0: MSB of horizontal scroll offset
	  if 1, horizontal scrolling will scroll another 256 pixels to the
	  right.  This can access a second horizontal page.

$2001 (PPU_Ctrl1)	PPU Control Register 1
	bit 7: Sets background to blue.
	bit 6: Sets background to green.
	bit 5: Sets background to red.
	bit 4: Sprite enable
	  if set to 0, sprites will be blanked.  Always blank sprites before
	  writing or reading PPU memory, or changing sprite parameters.
	bit 3: Background enable
	  if set to 0, the background will be blanked.  Always blank background
	  before writing or reading PPU memory.
	bit 2: Sprite leftmost column enable
	  if set to 0, blanks leftmost column of sprites.
	bit 1: Background leftmost column enable
	  if set to 0, will blank leftmost column of background characters.
	  this can elimate problems with scrolling.
	bit 0: Monochrome mode
	  write a 1 here to switch to a monochrome display.  Tint settings will
	  still tint the display.

$2002 (PPU_Status)	PPU Status Register
	bit 7: VBlank occured
	  Set to 1 when a VBlank occurs.  Any VBlank NMI routine must clear
	  this bit by reading sr before another VBlank can occur.
	bit 6: collision detection
	  This bit is set to 1 when any pixel in sprite 0 overlaps a pixel on
	  the background screen.  It remains set until the end of a VBlank.
	Reading this register also sets the Scroll Register ($2005) so that the
	next write will be a horizontal scroll value, and sets the PPU Address
	Register so that the next write will be the high byte.


$2003 (Sprite_Addr)	Sprite Attribute Memory Address Register
	Determines where in sprite attribute memory a DMA will start, or where
	in sprite memory a read/write from $2004 will be performed.  If you
	change one attribure byte of a sprite, change all four.




$2004 (Sprite_Data)	Sprite Attribute Memory
	Read or write to this address to access sprite attribute memory, after
	first setting the address to read/write to with $2003 (oamar).  After
	each access, $2003 increments by one.

$2005 (Scroll)		Scroll Register, Horizontal and Vertical
	The first write to scchv specifies horizontal scroll displacement, and
	the second, vertical.  To set vertical scroll larger than 240, use bit
	1 of ctrl_0 ($2000).  Horizontal scroll can be changed on the fly, but
	vertical scroll can only be changed during a VBlank.  To change vertical
	scroll during display time, change the base display address in $2006.

$2006 (VRAM_Addr)	Video RAM Address Register, High and Low Bytes
	Write here to set the address for accessing PPU memory (storing high
	byte first).  The first byte read from $2007 must be discarded.
	Blanking must be set before using $2006 or $2007.  During display time,
	$2006 holds the current display address.  If written to during display,
	vertical scroll will be ignored, so you must set $2006 to take this into
	account.  Before the end of each VBlank, write a pair of zeros here to
	restart display at the correct offset.

$2007 (VRAM_Data)	Video RAM Data Register
	After setting the address with $2006, and setting the autoincrement mode
	with $2000, data may be written or read from the PPU here.  $2006 is
	automatically incremented by the proper amount (1 or 32) every read or
	write.  When reading, the first byte is invalid, and may be discarded.

$4000 (WRA0)		Duty, Nonstop/Timed Flag, Amplitude/Envelope for Sound A
$4004 (WRB0)		Duty, Nonstop/Timed Flag, Amplitude/Envelope for Sound B
	bits 7-6: Specifies duty cycle (waveform).  00=12.5% positive,
	  01=25% positive, 10=50% positive (pure square), 11=75% positive.
	bit 5: 0=timed mode (turns off sound when length counter reaches 0).
	  1=nonstop mode (sound is continuous, envelopes repeat).
	bit 4: 0=envelope mode, 1=direct amplitude mode (see bits 0-3)
	bits 3-0: Envelope step speed - 1 (in 1/4 frames) or amplitude setting.

$4001 (WRA1)		"Sweep" (ramping pitch) Sound Register for Sound A
$4005 (WRB1)		"Sweep" (ramping pitch) Sound Register for Sound B
	bit 7: Sweep enable.  Set bit 3 to 1 (subtract) when sweep off (0).
	bits 6-4: Sweep speed - 1 in quarter frames (60ths of seconds: .25 to 2)
	bit 3: add/subtract mode (shift frequency left/right).
	  0=add (pitch decreases), 1=subtract (pitch increases).  In subtract
	  mode, sound won't stop unless frequency can be shifted below 7 (which
	  may not be possible if number in bits 0-2 is too high).
	bits 2-0: Number of bits to shift frequency each sweep cycle (0=none).

$4002 (WRA2)		Low 8 Bits of Sound A (square wave) Frequency Code
$4006 (WRB2)		Low 8 Bits of Sound B (square wave) Frequency Code
	Can be modified while sound running.  If below 7, sound turns off.
	frequency in hertz is 1789772.5/(16 x (frequency code+1)).

$4003 (WRA3)		High 3 Bits Of Sound A Frequency Code, Length Code
$4007 (WRB3)		High 3 Bits of Sound B Frequency Code, Length Code
	bits 7-3: Code for length of sound.  When this byte is written to,
	   counter starts with given value (so high bits of frequency can NOT
	   be modified while timed sound is running, or sound will restart).
	bits 2-0: High bits of sound A frequency.  If high bit (2) is set, and
	   sweep mode is "add", sound turns off (whether sweep enabled or not).

$4008 (WRC1)		Nonstop/Timed Flag, Envelope Length Data for Sound C
	bit 7: If 0, shortest of two timers is used.  if 1, sound is continuous
	  if length counters are not both 0 (which always turns sound off).
	bits 6-0: length - 1 in quarter frames (.25 to 32)


	  
$400A (WRC2)		Low 8 Bits of Sound C (triangle wave) Frequency Code
	Frequency in hertz is 1789772.5/(16 x (frequency code+1)).  Does NOT
	turn off sound if frequency code is below 7.

$400B (WRC3)		High 3 bits of Sound C Frequency Code, Length Code
	bits 7-3: Code for length of sound (as in WRA3 and WRB3, above).  Sound
	   is started by writing to this byte.
	bits 2-0: High bits of sound C frequency.

$400C (WRD0)		Nonstop/Timed Flag, Amplitude/Envelope for Sound D
	bit 5: 0=timed mode (turns off sound when length counter reaches 0).
	  1=nonstop mode (sound is continuous, envelopes repeat).
	bit 4: 0=envelope mode, 1=direct amplitude mode (see bits 0-3)
	bits 3-0: Envelope step speed or direct amplitude setting.

$400E (WRD2)		Maximum Frequency Code for Sound D (noise)
	bits 3-0: Determines the "sample clock frequency" (maximum frequency of
	  random frequencies making up noise).

$400F (WRD3)		Length Code for Sound D
	bits 7-3: Code specifying length of sound D (as for sounds A, B, and C).
	  Writing to this bytes starts sound playing.

$4010 (WRE0)		Sample Speed, Repeat/Single Shot, IRQ Enable for Sound E
	bit 7: set to 1 to enable an IRQ at the end of each sample playback.
	bit 6: 1=repeat sound upon completion, 0=play sound once.
	bits 3-0: Specifies sample playback speed (decoded by lookup table).

$4011 (WRE1)		Sound E (Delta Mod) Direct Data Output
	Bits 6-1: Holds data read from memory to be sent to the A/D converter.
	Samples are stored as single bits, each of which increments (1) or
	decrements (0) the amplitude of the waveform.

$4012 (WRE2)		Initial Address of Sound E Waveform Data
	Actual address is computed by $C000+(WRE2*16).

$4013 (WRE3)		Length of Sound E Waveform Data
	Store length of sample here.  Length in bytes is (16*WRE3)+1.  The
	duration of the sound will depend on the sample speed (in WRE0).

$4014 (Sprite_DMA)	Start Sprite DMA At Specified Page
	Writing a number to this address specifies the page number (high byte of
	address) from which sprite attribute DMA will start, and starts the DMA.

$4015 (Sound_Enable)	Sound Enable/Length Flag, IRQ Flag Register
	bit 7: reads setting of IRQ flag for sound D.
	bit 4: enables sound E (delta modulated samples).
	bit 3: enables/reads sound D (noise).
	bit 2: enables/reads sound C (triangle wave).
	bit 1: enables/reads sound B (square wave), as above for sound A.
	bit 0: set to 1 to enable sound A (square wave), or 0 to disable.  When
	  read, this bit shows if the length counter for sound A is running.

$4016 (Joystick1)	Game Controller Port 1
$4017 (Joystick2)	Game Controller Port 2
	Write a 1 then a 0 to the port, then each subsequent read will return
	a bit specifying the state of a certain button on the controller (1 is
	pressed, 0 is not pressed).  Write $40 to $4017 during initialization
	to disable CPU LSI internal IRQ.
	bit 7: right		bit 3: start button
	bit 6: left		bit 2: select button
	bit 5: down		bit 1: button B
	bit 4: up		bit 0: button A